In a display, an input/output signal has a wideband frequency. In particular, an intra-panel interface between a timing controller and data-driver integrated circuits (ICs) needs to support a variety of operating speeds according to the number of used driver ICs and the number of channels of the driver ICs. As a point-to-point high-speed interface having an operating speed of Gbps or more, such as a mini-low-voltage differential signaling (LVDS) interface, has been used lately, rather than a multi-drop interface, jitter characteristics of a signal of an intra-panel interface are gradually becoming important. To obtain low jitter, a used clock generation or recovery circuit should have low jitter, and also a voltage-controlled oscillator (VCO) and a PLL using the VCO should have a low-jitter characteristic. In the case of a ring oscillator, a delay of each delay cell is changed by changing a magnitude of current or voltage swing, and thereby a frequency of the ring oscillator is changed. A PLL using such a delay cell is inappropriate for a low-jitter PLL because the PLL has high sensitivity to supply voltage and its VCO has high noise.
An output frequency of an inductor/capacitor (LC) VCO is tuned by adjusting a value of a fixed capacitor or varactor, and a frequency tuning range is determined according to a ratio of a controllable capacitor to a parasitic capacitance. Here, to obtain a low jitter characteristic, a switch connected with a capacitor, etc. while supplying the LC VCO with a large amount of current should have low resistance. In this process, the parasitic capacitance increases, and the controllable capacitor to parasitic capacitance ratio may become 10 to 40 percent according to a common tuning range. Thus, to obtain an operating range having a highest-to-lowest required frequency ratio of 2 or more, that is, a controllable capacitor to parasitic capacitance ratio of 100 percent or more, two or more LC VCOs are necessary.